Thin gate dielectric reliability and integrity comprise one of the major challenges for the development and manufacturing of VLSI (very large scale integration) and ULSI (ultra large scale integration) semiconductor products. The development of reliable and high quality thin gate dielectrics requires research and time-intensive efforts to meet demands for smaller device geometries and better performance and reliability. As the thickness of the gate dielectric continues to be reduced to meet industry demands, continuous process improvements are necessary to meet yield and reliability criteria.
It is currently known to collect life stress data using a stress to measure the effects of lifetime-accelerated voltage and temperature conditions on thin gate dielectric layers. After the application of accelerated life stress conditions, the chips are tested again, and a significant increase in gate leakage from its initial value signifies degradation, such as dielectric breakdown.
A common problem with incorporating dielectrics, in particular high-k dielectrics, into integrated circuit devices is the presence of dielectric interface traps. Dielectric Interface traps are electrically active defects located at the dielectric interface with the semiconductor and gate electrode materials, that are capable of trapping and de-trapping charge carriers. For example, ultraviolet light may induce an increased density of electronic states or traps at semiconductor-insulator interfaces, or—in general—at all interfaces of two facing materials that possess different electronic properties. This locally enhanced density of states may cause generation/recombination currents via a combination of tunneling and field emission. Since integrated electronic entities become more and more sensitive upon miniaturization as far as signal accuracy is concerned, such effects are very undesirable. Above all, an uncontrolled increase of the density of interface traps may interfere with capacitors and transistors causing the destruction of memory content or severely limiting the reliable operation of the electronic entities of a memory device. In particular, the so-called data retention time of an electronic memory device may be drastically reduced, the retention time being defined as the time span a memory cell may reliably store a respective logical state.
A conventional approach for obtaining some limited dielectric interface trap data is the Capacitance-Voltage (CV) method. Unfortunately, the C-V method only senses interface traps at the dielectric/semiconductor interface. Moreover, the C-V method is difficult to apply to thin dielectric films (e.g. <4 nm equivalent oxide thickness (EOT)) particularly when high gate dielectric leakage is present. Another known approach is referred to as the Charge-Pumping (CP) method. Like the C-V method, the CP method is difficult to apply to thin dielectric films when high gate leakage is present.
Although the above described methods can generally be used to resolve interface traps at the dielectric/semiconductor interface when the gate leakage is relatively low, these methods are not capable of resolving traps at the gate electrode/dielectric interface. Without the ability to resolve the interface traps at the dielectric/semiconductor interface traps, gate dielectrics cannot be fully characterized, and as process development activities related to enhancing the reliability of dielectrics including gate dielectrics may be retarded. Accordingly, there is a need to provide a new approach to the measurement of interface traps for thin gate dielectrics that permits resolving the build up of interface traps at the gate dielectric/semiconductor interface from the build up of traps at the gate electrode/gate dielectric interface.